This disclosure relates generally to integrated circuit design, and more specifically to an iterative synthesis of an integrated circuit for attaining power closure while maintaining existing design constraints.
A typical integrated circuit design begins with a high-level circuit specification that details the function of the circuit design and the constraints of the design such as the area or physical size of the design, power dissipation, frequency, etc. The circuit function is translated to a logic design written in a hardware description language such as Very High Speed Integrated Circuit Hardware Description Language (VHDL). A synthesis tool generates or synthesizes a circuit or gate level design from the hardware description of the design. Because the initial synthesis seldom generates a design that satisfies the specified constraints, changes to the circuit design are necessary. These changes to the circuit design are made manually and can be time consuming, especially where there is a timing and power budget to satisfy. For example, changes made to the circuit design to alter its timing or area may adversely affect the power dissipation, leaving the circuit design over the power budget. Similarly, changes made to the circuit design to alter power dissipation may adversely affect the timing, leaving the circuit design not meeting the timing budget. In either case, several iterations of manual changes and measurements to determine how these changes affect existing design constraints, such as timing and power, are necessary before arriving at a design that satisfies the design constraints. An approach that can optimize an integrated circuit design for power while maintaining existing design constraints is presented.